This article is about the last summary article of Xilinx DPD, which is more general, but it is used to pay attention to the problem.
1) The DPD V2.0 document states that the processing bandwidth of the DPD must not be less than three times the signal bandwidth. The recommended bandwidth is 5 times the signal bandwidth. In the process of using the relevant tests and experiments, if the processing bandwidth of the DPD is only 3 times the signal bandwidth, the improvement effect of the DPD does not reach the reference value provided by the document, which indicates that the processing bandwidth of the DPD is still better than the performance of the predistortion. Great influence. In the case of multi-carrier, and the carrier is not continuous, the processing bandwidth required is larger. This cannot be ignored.
We know the output of the DPD to the downstream FR unit. In fact, we say 3 times or 5 times the signal bandwidth. If the bandwidth in the RF unit is less than 3 times or 5 times the signal bandwidth, then those passbands that we keep in the digital domain. The bandwidth is lost.
In summary, it is necessary to ensure that the link bandwidth after the DPD input meets the requirements of the DPD, and the feedback path is also satisfied.
2) DPD requirements for the size of the input signal. DPD can handle small signals, ie low power signals, but does not guarantee predistortion. If the DPD is operating in DCL mode and the signal is below -33dBFS, the software detects that the power value is not met and will not perform the DPD operation. However, the input signal can not be too large, in general, it does not exceed -15dBFS. This is to reserve margin for the predistortion signal to ensure that the signal does not overflow.
3) The amplitude requirement of the received signal. The size of the received signal should be -15dBFS. In order to make the DPD IP core work better, it is best to make TX Power and Feedback Power close.
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