The principle and application of PicoBlaze processor IP Core
Analyze the structure, principle and design scheme of 8-bit microprocessor IP core PicoBlaze in detail; introduce PicoBlaze's instruction set and debugging tool pblazeIDE, discuss PicoBlaze's programming scheme and application design examples; list several PicoBlaze application schemes.
1 Overview
PicoBlaze 8-bit microprocessor is an embedded dedicated IP Core designed by Xilinx for Virtex series FPGA, Spartan-Iitxi series FPGA and CoolRunner-II series CPLD devices. It solves the problem of Constant Coding Programmable State Machine (KCPSM). This module only occupies 76 slices of SpartanIIE, accounting for 9% of the resources of the smallest XC2S50E device, and less than 2% of the resources of the XC2S300E device. This module also includes a ROM composed of Block RAM for storing instructions, which can store up to 256 instructions. PicoBlaze only uses so few resources, but its speed can reach more than 40MIPS.
PicoBlaze provides 49 different instructions, 16 registers (8 for CPLD), 256 directly or indirectly addressable ports, and 1 maskable interrupt with a rate of 35MIPS. Its performance exceeds the traditional microprocessor composed of independent components, and its low cost makes PicoBlaze have a wide range of application prospects in the field of data processing and control algorithms. Since the programmable part is also embedded, PicoBlaze can be combined with subroutines and peripheral devices to complete special designs. The basic application framework is shown in Figure 1.
The PicoBlaze module is designed by the VHDL language and does not require pre-compilation. It can be directly embedded into a larger capacity device by the place and route tool; it can be considered that PicoBlaze takes up almost no resources, and a design can include multiple PicoBlaze. PicoBlaze is suitable for complex systems that do not require too much time, and can be designed simply.
Figure 1 IP Core application framework of the PicoBlaze processor
2 PicoBlaze principle and structure analysis
The internal structure of PicoBlaze 8-bit microprocessor is shown in Figure 2.
The PicoBlaze processor IP Core is composed of global registers, arithmetic logic unit (ALU), program flow control flags and reset logic, input/output (I/O), and interrupt controller.
Global registers: 16 8-bit global registers, s0～sf. The operation of the register is very flexible; no register is reserved for special tasks, and the priority of any register is the same.
Arithmetic and Logic Unit (ALU): Provides all the simple operations required by an 8-bit processor. All operations are performed with the operand provided by any register. If the operation requires two operands, another register is specified or an 8-bit constant value is embedded in the instruction. On the premise of not increasing the size of the program, it refers to any constant value irregularly, which enhances the characteristics of simple instructions. More clearly, ADD1 and INCREMENT instructions are equivalent. If the operation exceeds 8 bits, there is an option (increase or decrease) to choose from. Binary opcodes (LOAD, AND, OR, XOR) can manipulate and test binary numbers, and also include a set of SHIFT and ROTATE instructions.
Program flow control flag: the result of ALU operation affects the two flags ZERO and CARRY. Use conditional or unconditional program flow control instructions to determine the order of program execution. The JUMP instruction specifies an absolute address in the program space. The CALL instruction locates the program to the absolute address of a subroutine written in a piece of code, and at the same time pushes the return address onto the stack. The stack used by nested CALL instructions is 15 levels, which is enough for the program size.
Reset logic: The reset signal forces the program to return to the initial state, that is, the program starts to execute from address 00, the interrupt is shielded, the status flag and the stack are also reset at the same time, but the contents of the register are not affected.
Figure 2 PicoBlaze processor internal structure
Input/Output (I/O): PicoBlaze provides 256 input ports and 256 output ports. An 8-bit address value and a READ or WRITE strobe signal are provided by the port bus to specify the access port together. The port address value is either a definite value or specified by the contents of any register. When accessing a memory composed of distributed or block RAM, it is best to use direct addressing. When an input operation is performed, when the value on the input port is output with a READ_STROBE output pulse, it means that an input operation has been performed. *Xilinx specially designed the KCPSM2 module for Virtex-E devices, providing 1024 addresses and operating 32 registers.
Interrupt controller: PicoBlaze provides an interrupt input signal. As long as some simple combinational logic is used, multiple signals can be combined and applied to this interrupt. The program can define whether this interrupt is masked or not, the default value is that the interrupt is masked. An activated interrupt signal causes the program to execute the "CALL FF" instruction (FF is 256, the last location of the program memory), and then a section of the program defined by the designer for this purpose is executed. Generally put a JUMP instruction at this address to jump to the interrupt service routine. The interrupt process shields other interrupts, and the RETURNI instruction ensures that after the interrupt program ends, the mark and control instructions return to the original state.
Table 1 PicoBlaze processor instruction set
| Control program transfer instruction | Loop transfer instruction | Logical operation instruction | Input/output instructions |
| 81aa JUMP aa 91aa JUMP Z,aa 95aa JUMP NZ,aa 99aa JUMP C, aa 9Daa JUMP NC,aa 83aa CALL aa 93aa CALL Z,aa 97aa CALL NZ,aa 9Baa CALL C,aa 9Faa CALL NC,aa 8080 RETURN 9080 RETURN Z 9480 RETURN NZ 9880 RETURN C 9C80 RETURN NC | Dx0E SP0sX Dx0F SR1sX Dx0A SRXsX Dx08 SRAsX Dx0C RR s Dx06 SL0sX Dx07 SL1sX Dx04 SLXsX Dx00 SLAsX Dx02 RL sX | 0xkk LOAD sX,kk 1xkk AND sX,kk 2xkk OR sX,kk 3xkk XOR sX,kk Cxy0 LOAD sX,sY Cxy1 AND sX,sY Cxy2 OR sX,sY Cxy3 XOR sX,sY | Axpp INPUT sX,pp Bxy0 INPUT sX,(sY) Expp OUTPUT sX,pp Fxy0 OUTPUT sX,(sY) |
Arithmetic operation instructions | |||
Interrupt instruction | 4xkk ADD sX,kk 5xkk ADDCY sX,kk 6xkk SUB sX,kk 7xkk SUBCY sX,kk Cxy4 ADD sX,sY Cxy5 ADDCY sX,sY Cxy6 SUB sX,sY Cxy7 SUBCY sX,sY | ||
| 80F0 RETURNI REABLE 80D0 RETURNI DISABLE 8030 ENABLE INTERRUPT 8010 DISABLE INTERRUPT |
3 PicoBlaze's instruction set and debugger
Table 1 lists all the instructions that represent the PicoBlaze opcode in hexadecimal, where:
①"X" and "Y" represent registers, "s", the range is 0～F;
②"kk" stands for constant, "aa" stands for address, and "pp" stands for port address, both in the range of 00～FF.
pBlazIDE (Integrated Development Environment) is an integrated environment for editing, debugging and assembling the PicoBlaze assembler. It can be used to easily simulate the input and output of the written program, the change of the value in the register and the sequence execution process of the program instruction, which is convenient for checking the error of the program. The VHDL source code and debugger pBlazeIDE for the PicoBlaze processor IP Core application can be downloaded directly from the Xilinx website.
4 PicoBlaze application system design
The PicoBlaze processor IP Core used in Spartan-II and Virtex-E devices has an external RAM that can store 256 instructions to work together. If users need more program storage space to perform more complex operations, there are several solutions. 
*If the user's program exceeds 256 instructions, you can consider decomposing the design into several processes, each of which is completed by a separate PicoBlaze module (each with its own RAM). In some designs, one PicoBlaze is the primary (Master), and the other one or more PicoBlaze is the secondary (Slave). Dual-port distributed memory is a good choice for exchanging data between processors.
*You can choose to decompose a program with more than 256 instructions into two or more block RAMs, and use a selector switch to select the RAM that stores the instructions to be executed. The simplest is to use a one-of-two selector controlled by a flip-flop output to select RAM, as shown in Figure 3.
The disadvantage of this method is that the two-way selector occupies 8 slices, and the delay of program execution is increased, and the maximum execution rate of the program is reduced. A better method is to put the two-way selector in the RAM, and an instruction is stored in two 512&TImes;8 RAMs, and the switch signal and the 8-bit address signal are used to form a 9-bit signal to select the instruction to be executed. Figure 4 lists an example of using PicoBlaze to control the display of four seven-segment data tubes. The two on the left change from 0 to 99. The situation on the right is the same, and the change interval is 1s. But at the same time, only one counter increases, and the choice of which counter increases is controlled by the DIP switch input. 
Figure 4 PicoBlaze processor IP Core application design example
Concluding remarks
PicoBlaze is a typical 8-bit microprocessor. Compared with the traditional 8-bit MCU, it is a soft processor IP Core implemented by VHDL, which can be implemented on various FPGAs and CoolRunnerII CPLDs, and the design is flexible and convenient; therefore, PicoBlaze will be used in applications based on programmable logic and MCU Play an active role in the field. Its higher processing performance and less resource occupancy indicate its broader application prospects.
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