As a third-generation display, Organic Light EmitTIng Diode (OLED) has an LCD with excellent characteristics such as active illumination, fast response, high brightness, full viewing angle, DC low voltage drive, all solid state, and low environmental impact. Unmatched advantages have broad application prospects in mobile phones, personal electronic assistants (PDAs), digital cameras, car displays, notebook computers, wall-mounted TVs, and military fields, and thus have received widespread industry attention. OLED has developed from the original monochrome to the current full color, and at the same time put forward higher requirements for the drive circuit, from the initial gray-free monochrome static drive to color dynamic drive.
At present, the research focus of OLED is to develop high-stability devices to meet the practical requirements, but it is also important to study the driving technology to achieve high-quality dynamic display, because only a combination of good driving technology, improve the reaction speed and resolution, In order to show the excellent characteristics of OLED. However, the monochrome OLED display requires a high control precision of the driving voltage, and the color OLED display is more difficult to implement by accurately controlling the gradation of the RGB three primary colors at the same time. In order to achieve true color, the three primary colors of R, G, and B must each achieve 256 gray levels. The circuit described in the paper belongs to the full-color dynamic driving circuit, and will study and design its 256-level gray scale display and peripheral drive, which will provide a feasible technical solution for large-size OLED displays in the future.
1 drive control system design
The performance of the display depends on the material of the display on the one hand and the drive circuitry of the display on the other hand. The drive circuit system is an indispensable part to ensure the normal operation of the display, and plays an important role in the display performance. The difference of the drive circuit system will cause the display to display color, brightness, display gray level, response time, power consumption and other display parameters. The OLED display requires a dedicated control driver chip. Only the successful combination of the OLED screen and the driver control chip can promote the development of OLED and replace the LCD. However, at present, the hotspots of OLED research at home and abroad are mainly on devices and materials. There are relatively few researches on driver circuits and gradation control. The existing OLED driver circuits have low integration, and the scanning efficiency optimization for OLED characteristics is also not tall. Therefore, designing a high-performance OLED driver circuit has become an urgent problem to be solved in the display field. Based on the existing research, the paper designs a peripheral drive circuit with a resolution of 480 & TImes; 640 color OLED screen, and optimizes the 256-level gray scale implementation method to make it perfectly integrated with OLED, thus further pushing the OLED forward. development of.
1.1 OLED pixel unit circuit
For the implementation of the OLED drive control system, the key technology lies in data writing and scanning control. Figure 1 is a single-pixel dual-tube driving circuit. One TFT is used for addressing and the other is a current modulating transistor for supplying current to the OLED. In order to prevent the current change due to the change of the OLED turn-on voltage, a P-channel device is used, so that the OLED is at the drain end of the driving TFT, and the source voltage is independent of the voltage on the organic layer.
The Data Line is connected to the source of the addressing TFT. The Scan Line gates the address TFT. The contents of the data line are written to the storage capacitor CS by leakage current and temporarily stored as charges.
When Power Line is high, the source level of the driving TFT is high, and the charge on CS will gate the driving TFT, and its leakage current flows through the OLED display device to drive its light. The level of the data line determines the brightness and darkness of the pixel.
1.2 256-level grayscale display
The gray level of the image refers to the level of the brightness of the image, and the brightness of the base color is divided by the intensity, which is the gray level. The higher the gray level that the display can produce, the more colors and image levels are displayed. Moreover, the perception of the brightness of the human visual system is not only related to the intensity of the brightness itself, but also related to the lighting time and the lighting area. In a certain time range, the longer the lighting time and the larger the area, the human eye feels. The stronger the luminous intensity. Therefore, by using the "suspend" effect that the human eye is not sensitive to fast bright and dark flicker, changing the lighting time and area of ​​the illuminant to distinguish the brightness, a different gray level picture is formed, and the general gray level is formed. The higher the color and image level displayed, the softer the image and the more realistic the image hierarchy. High gray level and effective gray level modulation are extremely important for the development of high definition display. At present, an OLED display driver needs to solve the problem of gray scale accuracy.
OLED display can use traditional analog voltage control method to achieve gray scale. The problem is that there is a nonlinear relationship between brightness and data voltage, and there is a gradual and easy-to-control linear interval. Therefore, the analog voltage method is used to adjust the luminous intensity. It is difficult to accurately and efficiently achieve gray scale display of OLEDs, and the general trend now is to use digital drive circuits.
The difficulty of the digital driving circuit is that the operating frequency is much higher than that of the analog driving circuit. There are two main practical gray-level modulation methods at this stage. One is pulse width modulation, which is to control the duty cycle of the drive pulse; the other method is the subfield control method, which divides the illumination time into several subfields by 1:2:4:8:... Different subfields can be combined to achieve different gray levels. However, the pulse width modulation method has a complicated timing, and the display screen has a high response speed. However, the subfield method requires a higher driving frequency, which is difficult to implement for a high gray level.
Considering the compromise between frame rate and OLED screen display efficiency, the operating frequency of the driver circuit is at a reasonable level. Based on the pulse width modulation and subfield principle, the two methods are optimized, and 256 gray scales are adopted. The image data is realized by the method of bit time-division display, that is, for the input 8-bit pixel signal RGB, the gray-light display is achieved by assigning different display times to different bits of each color byte, so that the display time of each bit is 128:64:32:16:8:4:2:1, with its combination, you can get the sub-pixel illumination time corresponding to 256-level grayscale display, and realize visual 256-level grayscale, that is, 16.67 million color display. Achieve high quality display.
To achieve 256-level gray scale, the scan time of one pixel is divided into 19 unit time t, and the time occupied by the 8-bit gray data q[7:0] from high to low is 8t, 4t, 2t, t, respectively. t, t, t, t. In order to make the display time of different bits into a certain proportion, the erasing time of t/2 is introduced from q[3], q[2] introduces the erasing time of t/4, and d[1] introduces the erasing time of t/8. d[0] introduces the erasing time of t/16. As shown in Fig. 2, the blanking signal is generated by the control circuit for blanking. From this, the OLED screen brightness percentage λ = (8 + 4 + 2 + 1 + 1/2 + 1/4 + 1 / 8 + 1 / 16) / 19 = 83.9% is calculated.
1.3 FPGA Controller
Utilizing the advantages of FPGA processing speed and data width and the abundant resources available in the chip, peripheral drive control circuits are designed for OLED displays with resolutions of 480 & TImes; RGB & TImes; 640. Its main function is to provide scanning control signals to the OLED display and digital signal processing for OLED display data.
According to the structure and characteristics of the peripheral interface of the OLED display, the FPGA chip is used to design a peripheral drive control system to provide control signals for the OLED screen and to transmit the data signals to be displayed.
As shown in FIG. 3, the decoded image data is stored in a FIFO (First In First Out) buffer, and under the control of the main clock, the image data in the FIFO is loaded into a 16×8 data load register. When the 16 8-bit data load registers are full, they will be latched by a 144-bit latch and wait for the D/A converter module. At the same time, the FPGA controller will also generate the row-column shift clock under the control of the master clock. And the row and column scan start pulse, the generated clock and pulse enter the DC-DC conversion module.
1.4 Various control signal periods and frequencies
In order to enable the FPGA controller to operate at a reasonable drive frequency and increase the brightness of the display, the structure is in the form of standard cell blocks. For a display screen with a resolution of 480×3×640, a unit block is formed by 8×16 display pixel tubes, and 480×3 rows are grouped into 90 blocks, that is, each block is simultaneously composed of a group of columns. Drive 16 rows of pixels. When the column scan driving circuit is designed, 640 column electrode groups are combined into 80 blocks, and each block drives 8 columns of pixels in parallel.
The refresh rate of the OLED display is 60 HZ/s, that is, the time for displaying one frame of image is 1/60 s, which is set to T. Therefore, the period T of the line scan start signal stx is 16 667 μs, and the duty ratio is 1: 90; Since the 480 x 3 row electrode group of the OLED display is combined into 90 blocks, the gate time of each block is T/90, that is, 185.185 μs. And cpx and cpbx are a pair of inverted non-overlapping pulse signals with a duty cycle of 50%. When the pulse signal is high and low, there is a block line pixel strobed, that is, one in cpx and cpbx. There are two Block row pixels in the cycle that are gated, so the period of the row scan drive pulses cpx and cpbx is T/45, which is 370.370 μs.
Similarly, the column of the OLED display is divided into 80 blocks, the gate time of each column block is 2.315 μs, the period of the column scan start signal sty is 185.1 85 μs, and the duty ratio is 1:80. The column drive pulses cpy and cpby are also a pair of inverted non-overlapping pulse signals with a duty cycle of 50%. When the pulse signal is high and low, a block is gated. Since the gate time of each column block is 2.315 μs, the period of the column scan driving pulses cpy and cpby is 4.630 μs.
During each column block strobe, eight 8 bit data read in parallel from the FIFO enters the data latch latch. The data is latched once during each BLOCK strobe, so the period of the data latch signal Lock is 2.315 μs. Since the latching of the 144 data is performed when 16 8-bit data load registers are full, the period of the 16-bit shift register clock clk_reg is 0.145 μs. The speed of reading data from the FIFO must be the same as the speed at which data is loaded into the data load register. The period of the read clock clk_fifo of the FIFO is also 0.145 μs. The 0.15μs (6.896 MHz) is approximately 7 MHz, so the basic clock of the system is 14 MHz, which is generated by the external crystal of the FPGA. The read clock is divided by two of the base clock.
1.5 FPGA workflow
The FPGA processor is the core part of the design. The workflow is to read 8 8-bit pixel data in parallel from 8 FIFO buffers in each clk_fifo clock cycle. When the rising edge of the clock clk_reg arrives, the 16-bit shift The register is shifted, and its output is connected to the chip select terminals of 16 8-bit data load registers, so that 16 8-bit data load registers are gated one by one, and the data can be loaded into 16 8-bit data loads. In the register, the output of these 16 8-bit registers is connected to the input of the 144-bit latch. After the 16 clocks cllk_reg rising edge, the 16 8-bit data load registers will be loaded in sequence. At this time, the data latch signal Lock arrives, latching 144 data into the 144-bit data latch, and then the data enters. To the DA conversion module, convert to 16 analog quantities, send them to the OLED display, and complete the loading of a block data.
Under the control of the column scan drive pulses cpy and cpby, 80 blocks are sequentially gated, and during each block is gated, a shift register and latch of 144 data will be performed, when 80 blocks are locked. After the save, the loading of one line of data is completed. When the 80 blocks of the first row are displayed, the column scan start signal sty comes over and starts scanning from the first column. At the same time, under the action of the line scan drive pulses cpx and cpbx, the second row of pixels is Strobe, so, the data of 1 to 80 blocks of the second line will be loaded at this time, and so on, until the 90 lines of data are displayed, the line scan start signal stx comes, and the first line is re-strobed. , looping back and forth, displaying data in one frame.
2 simulation results
Altera's Cyclone III series chip EP3C10E144C8 was selected as the target chip, which was designed in Verilog HDL language. The Modelsim simulation was performed on the GX-SOPC-EDA-EP3C10-STARTER-EDK development board. The simulation results are shown in Figure 4 and Figure 5.
It can be seen from the simulation results in Fig. 4 that 80 sets of column scan pulses cpv and cpby control 80 blocks, and after 80 column scan pulses are completed, the column scan start signal sty pulse starts, and the next line is continued to be scanned. After 90 lines of scanning, stx comes to re-single the first line, according to this cycle, in line with the design requirements.
It can be seen from the simulation result of FIG. 5 that the input 8-bit pixel data is converted into gray scale data by the gray scale generation module. Taking the first input data 8 hff as an example, the display time of each bit is 128:64:32:16:8:4:2:1, and different combinations thereof realize the function of 256 levels of gray.
3 Conclusion
Based on FPGA chip, a driving circuit of true color OLED display with resolution of 480×RGB×640 is designed. Based on the traditional subfield principle and the pulse width modulation duty cycle to realize gray scale, it is optimized by R. , G, B single-primary pixel time-division display method, achieving 256-level grayscale function. Through simulation and software and hardware co-simulation verification, the functions required by the design are realized. The 256-level gray scale implementation method is simple and flexible, which reduces the requirement of the FPGA driving frequency, and has high practical value for the application in the high-brush rate, high-resolution, high-gray display device. The circuit system can realize the transmission of full-color real-time moving images of OLED display, and provides technical support for OLED as a large-sized display in the future.
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