CPU terminology-3

IMM: (Intel Mobile Module, Intel prohibits promotion (advertising automatic filtering) module) Intel developed a processor module for notebook computers, integrated CPU and other control devices.

Instructions Cache: (instruction cache) due to the slow system main memory, when the CPU reads instructions, it will cause the CPU to stop waiting for memory transfer. The instruction cache is to add a fast storage area between the main memory and the CPU. Even if the CPU does not request the instruction, the main memory will automatically send the instruction to the instruction cache. When the CPU requests the instruction, it can be directly from the instruction cache. Read out, no need to access the main memory, reducing the CPU's waiting time.

Instruction Coloring: A technique for producing predictive execution instructions. Once a prediction is determined by a corresponding instruction, the processor will process the same instruction for the same type of determination.

Instruction Issue: This is the first CPU pipeline that receives the instruction sent by memory and sends it to the execution unit. IPC (Instructions Per Clock Cycle) indicates the number of instructions that can be completed in one clock cycle.

KNI: (Katmai New Instructions, Katmai New Instruction Set, SSE) Latency is more difficult to understand literally. In fact, it means that the clock cycles required to fully execute an instruction, the less the latency, the better. . Strictly speaking, the incubation period includes the entire process from receipt to delivery of an instruction. Most of today's x86 instructions require about 5 clock cycles, but some of these cycles are overlapped with other instructions (parallel processing), so CPU manufacturers advertise the latency longer than they actually are.

LDT: (Lightning Data Transport, lightning data transmission bus) K8 uses a new data bus, FSB 200MHz or more.

MMX: (MultiMedia Extensions, Multimedia Extensions) The earliest SIMD instruction set developed by Intel enhances the speed of floating point and multimedia operations.

MFLOPS: (Million Floationg Point/Second, Millions of floating-point operations per second) A unit that calculates CPU floating-point capabilities, based on millions of instructions.

NI: (Non-Intel, Non-Intel Architecture)

In addition to Intel, there are many other manufacturers that manufacture compatible x86 systems. Due to patent issues, their products are not the same as Intel, but they can still run x86 instructions.

OLGA: (Organic Land Grid Array) A chip package.

OoO: (Out of Order) One of the characteristics of the Post-RISC chip is that it can perform calculation tasks in the order provided by the program. It is an architecture that speeds up the processing of the processor.

PGA: (Pin-Grid Array, pin grid array) A form of chip package, the disadvantage is the power consumption.

Post-RISC: A new type of processor architecture whose core is RISC and its periphery is CISC. It combines the advantages of both architectures with advanced features such as predictive execution and processor renaming, such as Athlon.

PSN: (Processor Serial numbers, processor serial number) A set of numbers that identify the characteristics of the processor, including the primary frequency, the production date, and the production number.

PIB: (Processor In a Box, boxed processor) CPU products officially released on the market are usually more expensive than bulk devices shipped by OEM (Original Equipment Manufacturer) manufacturers to the market, but only PIB owns Manufacturer's formal warranty rights.

PPGA: (Plastic Pin Grid Array, a plastic needle matrix package) A chip package, the disadvantage is the large power consumption.

PQFP: (Plastic Quad Flat Package) A chip package.

RAW: (Read after Write, read after write) This is an error caused by the out-of-order execution of the CPU. That is, before the necessary conditions have been established, the result has been written first, resulting in an error in the final result.

Register Contention: A conflict that occurs when another instruction requisitions this register when the last write back task of the register was not completed.

Register Pressure: The number of registers required to execute the software algorithm is limited. For the X86 processor, the lack of registers has become its biggest feature, so AMD would like to increase the number of registers in the next-generation chip K8.

Register Renaming: (Register renaming) Repositions an instruction's output value to an arbitrary internal register. On the x86
In the architecture, this kind of situation often appears, such as: When a fld or fxch or mov instruction needs the same target register, it is necessary to use the register renaming.

Remark: (chip frequency re-identification) chip manufacturer to facilitate their own product rating, most of the CPU are set to be able to freely adjust the multiplier and FSB, it is selected in the same batch of CPU is good to be higher Level one, where the performance is less well-targeted, is done within the factory and is a legitimate method of frequency positioning. But after leaving the factory, the dealer overclocks the low-end CPU and puts a new label on it. The illegal frequency positioning of a high-end CPU is called Remark. Because manufacturers have the power to change their products, and dealers do this is copyright infringement, do not think that only software is copyrighted, hardware also has copyright.

Resource contention: When an instruction needs registers or pipes, they are used by other instructions and the processor cannot respond immediately. This is a resource conflict.

Retirement: When the processor executes an instruction, it automatically removes it from the scheduling process. If the instruction is only completed, but it remains in the scheduling process, it is not regarded as retiring.

RISC: (Reduced Instruction Set Computing) A short instruction length computer that runs faster than CISC.