As the complexity of system-on-chip (SoC) continues to increase, the challenges posed by the convergence of software and hardware development can not be underestimated. These powerful systems are now a mix of sophisticated software, firmware, embedded processors, GPUs, storage controllers and other high-speed peripherals. Higher functional integration combined with faster internal clock speeds and complex high-speed I/O means that providing a fully operational and fully-proven system is harder than ever.
Traditionally, software verification and debugging and hardware verification and debugging have been two different worlds. Usually, the software team and the hardware team are separate. The former focuses on the software execution inside the programming model, while the latter is debugged in the hardware development framework. The relationship between clock cycle precision, parallel operation and debug data backtracking original design is the key. In theory, after thorough debugging, the software and hardware should work together without errors. However, in the actual environment, there are not many cases of error-free cooperative operation, which is why it often leads to an increase in key costs and a delay in the product development cycle.
To achieve greater integration at a reasonable cost and timeframe, the industry must move to new approaches: design insights. In other words, if we want to be able to continuously validate and debug these systems efficiently, engineers must be designed in advance to provide a comprehensive view of the system. The key is to be able to understand the temporary relationship between the various behaviors covering the hardware and software domains. This article describes a way to debug an SoC using an embedded instrument, demonstrating that the entire system can be debugged faster and more efficiently by integrating hardware debug views and software debug views.
Build test bench
The SoC shown in Figure 1 consists of a 32-bit RISC instruction set processor and an AMBA APB peripheral bus connected to the AMBA AHB system bus. The SoC also includes a DDR2 memory controller, a Gigabit Ethernet network adapter, a Compact Flash controller, a VGA controller and multiple low-speed peripheral interfaces. The SoC runs the 4th edition of the Debian GNU Linux operating system, which runs the v2.6.21 kernel. The processor core operates at 60MHz, the DDR memory controller operates at 100MHz, and other I/O peripherals operate at a fundamental frequency between 33MHz and 12MHz. The entire SoC is implemented on the Virtex-5 development board.
Figure 1. SoC Baseline Test Bench
Overall, the system is a full-featured computer that provides terminal-based user access, the ability to connect to the Internet, run applications, install file systems, and more. These features of the SoC create complex debugging scenarios that put pressure on the functionality of hardware debugging facilities and software debugging facilities. In most cases, critical operations cover both hardware and software.
Debugging infrastructure
Processor core developers typically provide debugging infrastructure, either a fixed set of cores or a core set of configurable plugins. Either way, the debugging infrastructure becomes part of the core of being manufactured. The debug software then uses this infrastructure to provide debugging features for software developers.
Similar to most modern processors, such as Intel processors, AMD processors, IBM processors, Oracle processors, and ARM processors, the processor core highlighted here supports a basic set of debugging features. In this example, a "back door" accessible through JTAG allows a software debugger (such as GDB) to read and write to the memory in the system to detect the operating state of the processor. Through these mechanisms and access to the original software source code, GDB and other software debuggers can provide software breakpoints, single-step operations, variable value checking, stack traces, initial conditional configuration, alternate memory values, and recovery functions.
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