Blackfin is a new type of embedded processor introduced by Analog Devices. It is designed to meet the current computing needs of the audio, video, and communications applications and reduce power consumption. The ADSP-BF533 and ADSP-BF561 are representative DSP processors in the Blackfin series. This article will give some introduction on the application of BF533/BF561 in network multimedia.
one. Typical application of Blackfin series DSP:
Automotive Image System
Broadband Wireless System
Multimedia Consumer Electronics
Digital video recorder
Multi-channel VoIP
Security and monitoring
Set top box
video conference
two. Blackfin Series DSP Application Trends
The demand for DSPs in multimedia applications is changing. Currently, the market demand for the following products has gradually emerged: wireless, multimedia product applications, wireless local area networks, home gateways, and other consumer products; and the demand for products that require high-speed signal processing in automotive and industrial applications is also growing. The application of multimedia is gradually becoming networked and diversified. The current DSP needs to meet the market demand for rapidly growing products supporting multiple multimedia formats:
Video: WMV ver.9, H.264, MPEG-4, MPEG-2, MJPEG
Audio: WMA Pro ver.9, MP3, MP3 PRO, AAC, Dolby Digital, DTS
Speech: G.711, G.728, G.729AB, G.723.1A, AMR
Wireless Communication: WLAN 802.11b, GSM/GPRS, EDGE & 3G
Traditional programmable architectures have been unable to meet the requirements of signal processing that currently have special requirements. The solidified ASIC chip can not meet the cost, adaptability and rapid market requirements of current multi-standard product applications. The RISC/DSP-based architecture now has enough processing power to meet the needs of the broader audio and video products market.
three. Blackfin series DSP main features
The Blackfin series dsp core can reach up to 756MHz/1,512MMACs and can support multi-channel audio and VGA/D1 video multimedia applications. Enhanced dynamic power management with 0.8V core power to fully extend battery life in handheld applications. The ADSP-BF533 has a 600MHz clock frequency and 1.2GMACS (billion times multiply-accumulate operations per second) operation speed; the low-cost ADSP-BF531 has 300MHz/600MMACS (millions of multiplications per second) performance. Both Blackfin processors combine industry-leading digital signal processing (DSP) performance and microprocessor (MCU) functionality and support embedded operating systems for today's embedded audio, video and communications applications for high-speed computing and low power Consumption requirements. The ADSP-BF533 consumes only 280mW at a 600MHz performance level. In order to take full advantage of the dynamic power management capabilities of the Blackfin architecture, the processor integrates an on-chip switching regulator that uses a 2.25 V to 3.6 V external supply voltage to generate a programmable core operating voltage of 0.7 V to 1.2 V. Reduced overall costs and saved external power components.
These new Blackfin processors also support embedded operating systems such as embedded Linux, ThreadX, and Nucleus operating systems. In addition, the video optimization features within the Blackfin processor enable fully programmable D1/VGA real-time video and multi-channel audio processing without the complexity or inflexibility of specialized hardware or heterogeneous dual-core solutions. With this programmable Blackfin processor, users can develop products quickly to market and easily support emerging multimedia formats such as MPEG-4, H.264 and Windows Media.
four. The internal structure of Blackfin series DSP
The BF533 has a high degree of integration and integrates a rich peripheral interface, as shown in Figure 4-1:
Figure 4-1 BF533 peripheral module
Robust peripheral interface supports ITU-R 656 video data format
Two dual-channel full-duplex synchronous serial ports support eight stereo I2S channels
12 DMA channels support one and two-dimensional data transmission
The memory controller can be tightly connected to a variety of external memories such as FLASH, SDRAM, SRAM, and ROM
3 timers that can support PWM core pulse width/time calculation mode
IrDA-enabled UART
SPI compatible port
Real clock
Watchdog timer
Debug/JTAG interface
PLLs supporting multiples of 1x to 63x frequency
Blackfin processor DSP kernel structure, as shown in Figure 4-2:
The Blackfin DSP core includes two 40-bit arithmetic logic units (ALUs), two multiplier/accumulators (MACs), four video ALUs, and a shifter. Each computing unit performs different types of operations: the ALU performs arithmetic and logic operations; the multiplier performs multiplication, multiplication/addition, and multiplication/subtraction operations; the shifter performs logical shifts, arithmetic shifts, bit compression and decompression operations; The ALU performs a single-instruction-processing multiple-data (SIMD) logic operation, which is based on 8-bit data.
The calculation unit inputs/outputs data through the data register group. The data register set contains eight 32-bit registers. Each 32-bit register can be seen as two independent 16-bit registers. For example, the register R0 can be regarded as consisting of two 16-bit registers R0.H and R0.L. There are also two 40-bit accumulators Acc0 and Acc1 in the register bank. They are special registers for ALU operations and are mainly used for multiplication and addition operations.
The program controller controls the flow of instruction execution, which includes the alignment and decoding of instructions. The program controller supports conditional branching, conditional subroutine calls, and zero overhead cycles. The circular buffer stores the instructions to be executed.
In the current embedded multimedia applications, there are some solutions that use multi-processing technologies. The general structure is shown in Figure 4-1. The dual-core engine is seamlessly connected through dual-port RAM to form a comprehensive hardware/software platform. , You can run the operating system and applications using the standard API:
The same multi-processing technology can also be used on the Blackfin family of DSPs. In this architecture DSP is mainly responsible for media processing and signal processing; RISC mainly completes control, packet processing and so on.
Actually, the Blackfin series processor is not just a simple DSP. It is a high-performance dual-MAC processor, and it has additional features common to other similar microprocessors, which can be compared with those of ordinary RISC MCUs. Figure 4-2 shows the comparison between the OMAP architecture processor and the Blackfin processor series:
The OMAP series processors have dual-core architectures for ARM and DSP. The ARM core is responsible for running embedded operating systems and application software. The C5X is responsible for video and image processing. The Blackfin family of processors can simultaneously run embedded operating systems, upper applications, and general signal processing.
The BF561 in the Blackfin series DSP processor adopts a symmetric multi-processing architecture. Two BF533 DSP cores are integrated in one BF561 chip, as shown in Figure 4-3.
BF561 frequency up to 600M, and supports parallel processing to ensure its powerful digital signal processing capabilities, and supports low voltage and low current power supply. It can meet the performance and power consumption requirements of multi-functional digital consumer products.
The BF561's flexible multi-processing architecture supports multiple operating modes, as shown in Figure 4-6:
In the first mode (DSP + RISC), two cores inside the BF561 can be divided into one for signal processing; the other can be used to run the operating system, Ethernet transmission, and other control-related tasks. .
In the second mode (PURE DSP), one task can be given to two different cores for signal processing. Odd-numbered frames are completed by Core A, even-numbered frames are completed by Core B, or two different tasks. It can also be done by Core A and Core B separately. The performance of the processor has been doubled.
Application Example Based on Blackfin Series DSP
(1) IP set-top box
Embedded IP set-top box solution based on Blackfin+MCU/uClinux architecture:
Among them, 32-bit RISC MCUs are responsible for running embedded linux, handling wireless LAN/Ethernet transmission, hard disk storage, audio codec, file management, and control. The media stream received by the MCU from the network can be stored to the hard disk or passed to the BF533 through the SPI interface (up to 12 Mbps). The BF533 is responsible for the video encoding and decoding of the H.264@D1 format. The function module is shown in Figure 5-2.
(2) Visual VoIP Phone
With the rapid development of multimedia technology and communication technology, a single voice communication method cannot fully meet people's communication requirements. People urgently need to improve communication methods. The visual IP phone can use the network to transmit the images and voices of the two parties in real time in both directions to achieve face-to-face communication. With the current popularity of broadband access, it provides a good foundation for the promotion and development of video telephony.
Here is a video VoIP phone solution based on BF533 and arm9 (400MHz) MCUs:
Hardware aspects:
SAMSUNG S3C2440 (400MHz)
ADI BF533 (600MHz)
TFT LCD (3.5" or more)
FLASH
SDRAM
CCD camera
Video A/D
Audio A/D
Audio D/A
Ethernet MAC+PHY chip
Software:
Arm9(400MHz) support:
Operating System (Linux)
Video decoding (H.264, MPEG4)
Audio decoding (G.711, G.723.1, G.729, MP3)
Ethernet communication (TCP/IP stack, etc.)
H.323 protocol stack
Graphical user interface (GUI)
ADI BF533 supports:
Video capture code (H.264, MPEG4)
Audio capture code (G.711, G.723.1, G.729)
Echo cancellation
By using arm9+BF533 and related software support above, we can achieve the following functions:
Audio and video intercom over LAN and WAN
Multimedia entertainment features: Can play MPEG4 video and MP3, WMA music
Support email service
Support SMS, MMS SMS
Support software disk, handwriting input
External keyboard and mouse
The basic structure and core technology of videophone:
The basic structure of videophone includes:
Video input/output module, video codec
Audio input/output module, audio codec
Delay unit
Data processing, storage unit
System Control Unit
Web Interface Unit
2. The core technology of videophone:
Voice and video compression technology is the core technology of video telephony. As a communication terminal product, videophone must ensure good enough voice and video quality while occupying as little bandwidth as possible. The goal of the development of voice and video compression technology is to maximize the compression rate while ensuring the quality of voice and video after compression.
2.1 Speech coding technology
Voice communication is the most basic function of videophone. Due to the limitation of network conditions, videophones cannot occupy too much bandwidth. In order to meet the requirements of low bit-rate voice communications, ITU-T introduced the G.72X series of voice compression standards. Among them, G.723.1, G.728, G.729 and G.729A have been widely used in IP telephony. Different voice compression standards use technologies that provide different code rates, delays, and voice quality.
2.2 Video Coding Technology
The original video data needs to occupy a very high bandwidth. If it is necessary to transmit over the network, it must be ensured under certain premise of image quality to reduce the bit rate of the video data by compression techniques to adapt to different network conditions. Therefore, the video compression algorithm Efficiency determines the image quality and application prospects of video telephony.
Currently, in network monitoring and video on demand applications, video compression algorithms in the MPEG4 format are popular, and their code rates generally range from hundreds of Kbps to 1 Mbps. The low bit rate video compression standard introduced by ITU-T has played an important role in promoting the development and practical application of video telephony. H.261 is the first low bit rate video compression standard introduced by ITU-T. The code rate is p×64 kbit/s, where p=1 to 30, and the image format is CIF(352*288) and QCIF(162*144). ). At present, the H.264 algorithm can compress the same video to a lower bit rate, but its computational complexity is also greatly increased. It is believed that with the further improvement of DSP chip processing capabilities, the application of H.264 network video transmission will become more and more popular.
2.3 Communication Protocol
In order to ensure reliable communication of the videophone over the network, different terminals must run a unified communication control protocol to ensure mutual cooperation.
The ITU-T H.320/323 standard targets different networks, different network interfaces, different signaling processes, and optimized packet structure to accommodate different networks. The reuse agreement stipulates the packaging standards for video data, voice data, etc. The role of the control protocol is the communication between terminals, such as negotiation of video coding standards, negotiation of voice coding standards, and negotiation of channel bandwidth. Ethernet-based video phones typically use the H.323 control protocol.
3. Arm9+BF533 based solution
At present, ARM9 series processors have been widely used in handheld terminal applications such as PDAs, Smart Phones, and PMPs, and they have obvious advantages in video phones.
3.1 Speech and Video Coding
Speech and video coding require very strong mathematical computing capabilities, usually using an ASIC chip or a general-purpose DSP. ADI BF533 has a very strong computing capacity, fully meet the requirements of video compression, and has a very strong flexibility, through the software can be flexible to meet the requirements of product upgrades and adjust the compression rate for network bandwidth.
The BF533 accepts the video stream collected from the CCD sensor, compresses the audio stream collected from the Microphone, compresses it, and transmits it to the ARM9 chip through the SPI interface.
3.2 Speech and video decoding
Arm9 is able to directly decode and play audio and video at a frequency of 400MHz without having to send it to the DSP for decoding and playback, greatly reducing the burden on the DSP and the complexity of the system.
3.3 Network Transmission and Communication Protocol
Arm9 can support TCP/IP protocol through embedded Linux, and can extend Ethernet through local bus.
Linux can also implement the H.323 protocol and consume very little CPU power.
3.4 User Interface
The ARM9's built-in LCD controller can support higher resolution TFT LCDs for displaying local and decompressed images. And based on Linux, Huaheng Technology has generally implemented support for embedded GUIs such as Microwindows and Minigui on the arm9 platform, and can achieve a more complete graphical user control interface.
In addition, arm9 built-in 1 to 2 USB ports, you can connect U disk for data exchange, or expand the USB keyboard and connect to the host through the USB interface, configure the videophone work mode. And can support RTC, Watchdog, and through GPIO expansion buttons.
It is not difficult to see from the above applications that the application of ADSP series processors in embedded network multimedia has significant advantages: high cost performance, small size, low power consumption, and simple design of peripheral interface circuits.
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