Abstract: Successfully developed the deposition and etching processes for super-thick dielectric films, electroplating of ultra-thick metallic copper, and chemical mechanical polishing. The super-thick metallic copper integrated inductor was fabricated using a CMOS-compatible copper interconnect single damascene process. The ultra-thick metal copper inductor has a uniform inductance value in the frequency range of 1 to 3 GHz and a Q value of 11 at 2.5 GHz. Furthermore, the influence of the number of coil turns, metal line width, and metal spacing on the inductance value and Q value was further studied.
In a radio frequency integrated circuit (RFIC) process, a silicon substrate spiral inductor (SIOS) is a critical part of the performance of many RF integrated circuits. Using a high Q value on-chip integrated inductor can improve the reliability and circuit design efficiency of RF module circuits. . One method commonly used to increase the Q of an inductor is to use a high-impedance substrate (2 kΩ•cm) to reduce the substrate's parasitic effects, but this approach is incompatible with traditional CMOS processes. Because in the CMOS or BiCMOS process, the resistivity of the substrate generally does not exceed 30 Ω•cm [1-3]. Another way to increase the Q value of the integrated inductor and is compatible with CMOS is to use copper interconnect technology to reduce the metal coil resistance. Because the Q value of the inductor is inversely proportional to the metal coil resistance, reducing the resistance of the metal line is the most effective way to increase the Q value [4-5]. Increasing the metal line width and thickness can reduce the resistance, but increasing the line width will affect the degree of integration. At the same time, it will also increase the parasitic capacitance, thus affecting its operating frequency and increasing the coupling between the inductor and the substrate. In the process, the thickness of the metal can not be increased without limit. When the thickness of the aluminum wire exceeds 3 μm, the lines are easily broken, and at the same time, the etching process will bring great challenges.
Due to its low resistivity (1.7 μΩ•cm), copper can theoretically replace aluminum as an inductor and effectively reduce the metal coil resistance. In the current industry, the damascene structure of the copper interconnects and the chemical mechanical polishing (CMP) planarization are used instead of the etching process, so the copper lines can be made thicker than the aluminum lines, and the metal coils have lower resistance. This paper studies the process of ultra-thick metal copper interconnects, prepares a thick copper inductor that is fully compatible with CMOS technology, and conducts a systematic test of its performance.
1 Process flow and process characteristics
1.1 Process flow
Considering the effects of inductor size, Q value, reliability, process complexity, and compatibility, we use a thick insulating substrate structure. Although the coils of this structure have no sacrificial layer structure, the performance of the coils can be obtained due to the weakening of the parasitic effect of the thick insulating layer on the substrate. Using a metal top layer (MTT) far from the substrate as the inductor can reduce the losses caused by the electromagnetic field coupling between the substrate and the metal layer in the substrate. The specific process method is to adopt the copper single damascene process, which is divided into metal layers and mainly includes five process modules: MTT, VT2, MT, VT1 and Mx.
1.2 Process Characteristics
Thick Tip Metal (MTT) with low resistivity and far from the substrate is used as the inductor. The technical difficulties existed in the process include the deposition and etching of super-thick dielectric films, the electroplating (ECP) and CMP of extra-thick copper, and the inhibition of the diffusion of copper atoms in silicon and silicon dioxide. This article uses 3.3 μm ultra-thick metal copper as the on-chip spiral inductor. The ultra-thick Cu layer design rules the minimum metal line width / minimum metal spacing of 2.5 μm / 2 μm, the maximum metal width of 45 μm, the most critical process It is an ultra-thick, thick-line etching and a large-area copper CMP.
1.2.1 Top Metal (MTT) Etching Process
The top layer metal (MTT) dielectric film was plasma enhanced chemical deposition (PECVD) TEOS 3.3 μm. After photolithography, different line width patterns were etched using an AMAT eMax etching device. The etching gas was C4F6. Figure 1 shows the topography of different line widths after etching. It can be seen from the figure that the trenches with 2.5 μm line width and 15 μm line width are well-formed after etching, and a uniform Trench bottom is obtained. The amount of overetching at the bottom is 1 000 to 1 100 Å.
1.2.2 CMP Process for Top Thick Copper (MTT)
Since different patterns (different line widths and spacings) have different surface topographies after performing ECP process, the metal thickness and the Dishing condition of each graphic area after CMP are also different, as shown in Table 1. Metal thickness and Dishing for various line widths are within the process specification.
Figure 2 shows the XSEM after the PVD, ECP, and CMP planarization processes. As can be seen from the figure, the top metal thickness is greater than 2.9 μm. At the same time, the design value is 10 μm for the inductor and the top and bottom line widths after etching and CMP are 10.000 μm and 9.743 μm, respectively. Both the thickness and width of the metal wire meet the design criteria and the groove morphology is good. The difference between the center (a) and the edge (b) is small, indicating that the etching and CMP uniformity are both good.
2 Inductor Performance Results and Discussion
2.1 WAT Test
In this paper, the MTT (Thick Top Metal) Meander-Fork structure of 3.3 μm metal layer has been tested electrically. The Meander square resistors with 2.5 μm line width, 2 μm pitch, and 0.2 m length are shown in Table 2.
According to industry standards, the Rs of a structure with a metal width/pitch (W/S) of 2.5 μm / 2 μm is 5.21 mΩ/□, and the average value of Rs in this paper is 5.6 mΩ/□, which is slightly larger than the industry standard because of the crystal of ECP copper. Smaller particles, coupled with lower annealing temperatures after ECP, result in a slightly higher copper resistivity.
Figure 3 shows the leakage test results of the Meander-Fork structure (W/S = 2.5 μm/2 μm, Length = 0.2 m). The leakage current level is about 1×10-13 A. The process is normal within the industry standard specifications.
2.2 Inductance Test Results and Analysis
The inductive test system consists of an E8363B network analyzer and a microwave probe station that can test scattered S-parameters. The spiral inductor is placed between two GSG (ground-singal-ground) probes. The silicon substrate is grounded through the test clip from the back side during measurement. Use the formula to convert the measured scattering S-parameters into admittance Y-parameters, and then obtain the inductance and Q values. The inductance value is mainly affected by the geometric parameters (area, shape, width, pitch, number of turns) and process parameters (substrate resistivity, metal resistivity, substrate, and coil distance).
In this paper, RF testing of two layers of metal was performed to initially evaluate the three main parameters of the inductive performance: quality factor Q, series resistance Rs, and series inductance L. For the performance comparison of a single-ended inductor (frequency range 100 MHz to 5 GHz), the main structural parameters involved are Dout (inductor outside diameter), W (metal width), S (metal pitch), and N (inductor turns).
2.2.1 Inductance Performance Analysis of Different Inductance Turns N
Figure 4(a) is the Q value of a spiral inductor with different turns N (Dout = 200 μm, W = 10 μm, S = 2 μm). When the frequency Freq is less than 1.0 GHz, the input impedance of the on-chip inductor is dominated by inductive reactance, and the Q values ​​of the six curves almost coincide. The increase in N at this time has a negligible effect on the value of Q. As the frequency increases, the role of parasitic capacitance increases and the value of Q gradually increases. When the frequency Freq is greater than 1.5 GHz, the Q value begins to decrease. The reasons include: (1) As the number of turns N increases, Din becomes smaller, regardless of the loss of the metal coil, or the loss of the substrate increases [6]. (2) At high frequencies, the skin effect becomes significant and the number of turns increases, resulting in an increase in the series resistance Rs (Fig. 4(b)). (3) The increase in the number of turns also leads to an increase in the parasitic capacitance, which causes a peak increase in the electric field energy, resulting in a decrease in the Q value.
Fig. 4(c) is a graph showing the change trend of the inductance L with frequency with different coil numbers. It can also be known from the figure that the larger the number of inductance turns, the larger the inductance L is.
Figure 4(d) shows the relationship between the quality factor Q and the inductance L of the inductor and the number of turns N at a frequency of 1 GHz. When N ≤ 4.5, L increases linearly with N. When N > 4.5, the L change tends to slow, that is, increase N, and the influence on the inductance value becomes smaller.
In summary, analyzing the effect of different N on Q and L, it can be concluded that when the chip area is limited, the increase in the number of inductor turns has little effect on its low frequency applications. However, after the frequency increases, the effect of the parasitic capacitance becomes larger, and the increase of N contributes less and less to the L value. At this time, a hollow inductance structure with a small number of turns should be used.
2.2.2 Inductance Performance Analysis of Different Metal Spacing S
Figure 5 shows the effect of different inductor pitch S on the inductance values ​​L and Q of traditional structures (Dout = 200 μm, W = 10 μm, N = 3.5). From Fig. 5, it can be known that starting from the 2 μm pitch, the smaller the pitch, the lower the Q value and the larger the inductance value. This is because the decrease in the pitch causes an increase in the parasitic capacitance between the metal coils constituting the inductance, resulting in a decrease in the Q value. The reduction in the pitch results in an increase in the mutual inductance of the line segments constituting the inductance, so that the inductance value increases.
2.2.3 Inductance Performance Analysis of Different Wire Width W
Figure 6 shows the influence of different metal line widths W on the inductance L and Q values ​​(Dout = 200 μm, S = 2 μm, N = 3.5). As shown in Fig. 6(a), when the width of the metal conductor becomes smaller, the quality factor Q of the inductor tends to increase. The Q value increases to 11 at low frequency and then decreases at high frequency. The reason is that under the condition of constant outside diameter, the metal cross-sectional area will inevitably increase with increasing width, so that the series resistance will decrease and the Q value will increase. However, at higher frequencies, the series resistance rises due to the skin effect and proximity effects, resulting in a decrease in the Q value. The narrower line width (W = 2 μm) in Figure 6(b) has a larger inductance, which is due to the smaller cross-sectional area of ​​the coil resulting in greater mutual inductance and external flux [7]. The increase of the line width also affects the degree of integration, and at the same time generates parasitic capacitance, which affects its operating frequency and increases the coupling of the inductor and the substrate, resulting in a decrease in the Q value.
3 Conclusion
In this paper, a thick Damascene copper integrated inductor was fabricated using a single Damascene copper interconnect process. Developed key process modules for ultra-thick copper inductors, including deposition and etching of super-thick dielectric films, electroplating of ultra-thick Cu, and CMP processes. After etching, the trench morphology was good. Both thickness and line width meet the design criteria. The electrical test results of the prepared thick copper metal inductors show that the Q value of the inductor can reach 11 (2.5 GHz). In the range of 1~3 GHz, the inductance value is more uniform. Different coil turns, metal line widths, and metal spacing have different effects on the inductance L and Q values ​​of ultra-thick metal Cu inductors. The copper inductor developed by this method is fully compatible with CMOS integrated circuit technology and has broad application prospects.
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